Design of highly reliable RISC processors incorporating concurrent error detection/correction

RISC processors are being used extensively in a wide range of applications, particularly as embedded controllers. Many of the applications, however, are potentially safety-critical and impose a stringent requirement for high reliability. Although the reliability of devices can be improved by performing `burn-in´ procedures, where potentially weak devices are identified before they are incorporated into systems, these procedures can, unfortunately, reduce the life-span of good devices in the field. An alternative approach to improving overall system reliability is to use some form of redundancy. In this instance the effects of a fault can be masked, permitting the system to either degrade gracefully or remain serviceable until a repair can be implemented. The added advantage of using redundancy techniques is the ability to detect and possibly correct the effects of intermittent faults. The occurrence of intermittent faults is increasing as a result of reducing the physical dimensions of devices, lowering operating voltages and reducing noise margins. Field studies have indicated that non-permanent faults cause between 82-95% of system failures in the field