Title :
An integrated 33.5dBm linear 2.4GHz power amplifier in 65nm CMOS for WLAN applications
Author :
Afsahi, Ali ; Larson, Lawrence E.
Author_Institution :
Center for Wireless Commun., Univ. of California, La Jolla, CA, USA
Abstract :
An integrated linear 2.4GHz CMOS power amplifier is presented. With a 3.3v supply, the PA produces a saturated output power of 33.5dBm with peak drain and power-added efficiencies of 44.2% and 37.6%, respectively and has 40dB small-signal gain. By utilizing gm-linearization and digital pre-distortion, an EVM of -25dB is achieved at 26.4dBm with 22% PAE while transmitting 54Mbs OFDM. The chip is fabricated in standard 65nm CMOS and packaged in a 40-pin QFN package. The PA occupies 2.2mm2 active area.
Keywords :
linearisation techniques; power amplifiers; power combiners; wireless LAN; CMOS; WLAN applications; digital pre-distortion; efficiency 22 percent; gain 40 dB; gm-linearization; integrated linear power amplifier; size 65 nm; voltage 3.3 V; CMOS integrated circuits; CMOS technology; Distortion measurement; OFDM; Power amplifiers; Power combiners; Power generation; CMOS; Linearization; OFDM; Power Amplifier; Power Combiner; WLAN;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617401
