An efficient and practical architecture for high speed turbo decoders

Turbo codes not only achieve near Shannon capacity performance, but also have decoders with modest complexity, which is crucial for implementation. So far, efficient architectures for decoding of turbo codes have been proposed that are suitable for sequential processing. A novel architecture for a very high-speed turbo decoder is presented. The method makes parallel processing feasible. The performance of this decoder is illustrated and the tradeoff between speed and efficiency is discussed. It is shown that some decoders can run faster by some order of magnitude while maintaining almost the same processing load. A new structure for the interleaver is proposed, which makes the implementation of such a decoder feasible. It has been shown that the new interleaver structure can perform as well as other good interleavers.