Title :
A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS
Author :
Ryan, Joseph F. ; Calhoun, Benton H.
Author_Institution :
Univ. of Virginia, Charlottesville, VA, USA
Abstract :
This paper presents a sub-threshold Field Programmable Gate Array (FPGA) that uses a low-swing dual-VDD global interconnect fabric to reduce energy and improve delay. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-threshold FPGA using conventional interconnect and 22X less energy than an equivalent FPGA at full VDD.
Keywords :
field programmable gate arrays; integrated circuit interconnections; field programmable gate array; low-swing dual-VDD interconnect; size 90 nm; sub-threshold FPGA; Benchmark testing; Delay; Fabrics; Field programmable gate arrays; Integrated circuit interconnections; Synchronization; Table lookup;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5758-8
DOI :
10.1109/CICC.2010.5617466
