Task-farming of the detailed routing problem in VLSI design

A description is given of a technique for exploiting parallelism in the automatic routing process for hierarchical VLSI circuit design with particular emphasis on the techniques used in the detailed routing stage. The technique is used within a parallel routing system based on flexible general-purpose parallel hardware which can be used to speed up routing as well as other phases of the VLSI design process. The approach offers very substantial reductions in the time required to perform the computationally intensive routing phase of the chip layout process. The system is implemented in a suite of programs referred to as SPHIR (System for Parallel Hierarchical Routing) and is based on a general purpose MIMD architecture which is flexible enough to be optimally configured to speed up other phases of the design cycle as well