Modeling and simulation of transistor and circuit variability and reliability

Author

Asenov, A. ; Cheng, B. ; Dideban, D. ; Kovac, U. ; Moezi, N. ; Millar, C. ; Roy, G. ; Brown, A.R. ; Roy, S.

Author_Institution

Univ. of Glasgow, Glasgow, UK

fYear

2010

fDate

19-22 Sept. 2010

Firstpage

1

Lastpage

8

Abstract

Statistical variability associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. The major MOSFET statistical variability sources and corresponding physical simulations are discussed in detail. Direct statistical parameter extraction approach is presented and the scalability of 6T and 8T SRAM of bulk CMOS technology is investigated. The standard statistical parameter generation approaches are benchmarked and newly developed parameter generation approach based on nonlinear power method is outlined.

Keywords

CMOS integrated circuits; MOSFET; circuit reliability; circuit simulation; random-access storage; statistical analysis; 6T SRAM; 8T SRAM; CMOS scaling; MOSFET statistical variability sources; bulk CMOS technology; circuit reliability; circuit variability; integration; nonlinear power method; parameter generation approach; physical simulation; statistical parameter extraction approach; transistor; CMOS integrated circuits; Logic gates; MOSFET circuits; Semiconductor device modeling; Silicon; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4244-5758-8

Type

conf

DOI

10.1109/CICC.2010.5617627

Filename

5617627