Single Event Effect Mitigation in ReConfigurable Computers for Space Applications

Reconfigurable high performance on-board processing is a critical capability for many space systems. On board processing provides the ability to increase science data, provide real time decision making, and eliminates the latency associated with centralized downlinks and processing stations. Large SRAM based FPGAs provide a capable processing platform for these systems. Arrays of these devices can create systems providing 100´s of GFLOP´s of processing power. However, these devices have been shown to be susceptible to single event effects (SEE), and SEE mitigation techniques must be employed in order to reliably use them in space environments. Traditional methods such as triple modular redundancy (TMR) have been proven effective in mitigating SEE´s, but with a tremendous price in terms of area, power, mass, and speed. Many applications can not accommodate the costs associated with a full TMR approach. However, TMR is only one method of SEU mitigation. This paper introduces a novel approach to SEE mitigation for high performance reconfigurable computer´s (RCC). This approach eliminates the costs associated with full TMR SEE mitigation. The usage of this technique in processing systems increases the processing performance of a system by more than a factor of 2.5 over a full TMR only approach. For power, size, and mass sensitive space systems, this approach enables spacecrafts and missions that presently are not feasible