DocumentCode :
2792144
Title :
Simulation based test generation for scan designs
Author :
Pomeranz, I. ; Reddy, S.M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
2000
fDate :
5-9 Nov. 2000
Firstpage :
544
Lastpage :
549
Abstract :
We describe a simulation-based test generation procedure for scan designs. A test sequence generated by this procedure consists of a sequence of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. We consider the set of faults that can be detected by test sequences of this form, compared to the case where scan is applied with every test vector. The proposed procedure constructs test sequences that traverse as many pairs of fault-free/faulty states as possible, and thus avoids the use of branch-and-bound test generation techniques. Additional techniques are incorporated into this basic procedure to enhance its effectiveness.
Keywords :
automatic test pattern generation; logic simulation; logic testing; branch-and-bound test generation; faulty states; scan designs; scan-out operation; simulation based test generation; simulation-based test generation; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational modeling; Design engineering; Fault detection; Flip-flops; Logic circuits; Logic testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-6445-7
Type :
conf
DOI :
10.1109/ICCAD.2000.896529
Filename :
896529
Link To Document :
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