Title :
Testing of iterative logic arrays
Author :
Bhatia, Sandeep ; Albicki, Alexander
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
A method is presented to identify test vectors for iterative logic arrays (ILA). An ILA consists of several identical cells connected together in a regular configuration. The circuit regularity is exploited to regenerate the test vectors, applied at the boundary cells, within the array and thus propagate the test vectors to the entire array. This facilitates simultaneous testing of the entire circuit. The method covers a wide range of regular array structures like adders, multipliers, and interconnection networks
Keywords :
adders; logic arrays; logic testing; multiplying circuits; adders; boundary cells; circuit regularity; interconnection networks; iterative logic arrays; multipliers; test vectors; Adders; Circuit faults; Circuit testing; Equations; Iterative methods; Logic arrays; Logic testing; Multiprocessor interconnection networks; Tiles; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140697
