Systolic arrays for DFT computation-design and evaluation

A description is given of four systolic array designs for the computation of the DFT (discrete Fourier transform). The designs are simple, modular, expandable and characterized by high performance. The designs are representative cases of larger system families which can be structured by altering the ways that the input data and weight streams are becoming available to the processing cells. In accordance with the requirements of cost-effective silicon implementation and aims of systolic designs, only a very small number of different type cells is used, which because of their simplicity allow a high degree of system integration