Novel design of fast pipelined 2D QDCT on FPGA

The fast pipelined 2D QDCT designed on FPGA architecture is addressed in this paper. The key features of this are to modify and optimize the 1D DCT algorithm, and also merge the quantization together in the hardware that can be completely functioned in three pipeline stages. This leads to the speedup improved ~30% obviously and hardware resource saved efficiently by reducing arithmetic operators. The maximum operating frequency of the proposed approach is up to ~105 MHz on Xilinx Spartan 3E chip as XC3S500E target. These quantized coefficients based on JPEG standard is used to study compared with the conventional method of DCT and quantization resulting in the good agreements.