Self-test methodology and structures for pre-bond TSV testing in 3D-IC system

This paper presents a self-test methodology and test structures for testing Through Silicon Vias (TSVs) in 3D-IC system prior to stacking in order to improve overall yield. A Scan Switch Network (SSN) architecture is proposed to perform pre-bond TSV scan testing. In the SSN, novel self-test structures are proposed and integrated to detect TSV defects by stuck-atfault and delay-based tests. By exploiting the inherent delay characteristics of TSV, the variation of TSV-to-substrate resistance caused by TSV defects can be mapped to a path delay change and detected. Compared with prior works, the proposed test architecture addresses pre-bond TSV testing under an integrated test solution with low overhead. Test chip measurement and analysis are presented to verify the proposed self-test methodology and structures.