Title :
Separation measurement of parasitic impedance on a power electronics circuit board using TDR
Author :
Hashino, Satoshi ; Toshihisa, Shimizu
Author_Institution :
Tokyo Metropolitan Univ., Hachioji, Japan
Abstract :
Accurate identification of parasitic parameters on a printed circuit board (PCB) and establishment of a new design method by considering the parasitic components in a power electronics circuit will become major technological issues to promote power density of the circuit. This study focuses on time domain reflectometry (TDR) which is a high-speed transmission technique for the effective measurement of parasitic parameters on PCBs with complicated wiring arrangements. Identify of some individual parasitic inductances existing on a buck chopper PCB can be realized by utilizing an interaction between a reverse-side ground layer and a printed wiring of the PCB. And then, influence of stray capacitances formed between a heat-sink and power devices are mentioned in this paper. The accuracy of the measured parasitic inductances is verified by a comparison of experimental and simulation results.
Keywords :
electric impedance measurement; power electronics; printed circuits; time-domain reflectometry; PCB parasitic parameter measurement; PCB wiring arrangements; TDR; buck chopper PCB; heat sink; parasitic impedance separation measurement; power electronics circuit board; time domain reflectometry; Impedance; Inductance; MOSFET circuits; Printed circuits; Reflection; Semiconductor device measurement; Transmission line measurements; Extraction method of parasitic inductances; High power density converter; Time domain reflectometry;
Conference_Titel :
Energy Conversion Congress and Exposition (ECCE), 2010 IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-5286-6
Electronic_ISBN :
978-1-4244-5287-3
DOI :
10.1109/ECCE.2010.5618046