Synthesis methodology for built-in at-speed testing

We discuss a new synthesis flow, which offers the ability to do easy delay testing almost free in terms of its impact on speed and area compared to corresponding implementations with standard cells. The methodology uses matched delays in pre-charged PLAs and bundled routing to produce a completion signal, which is guaranteed to lie on all critical paths. We give a nondelay testing method for ensuring matched delays are correct, i.e. that all completion signals arrive after their corresponding data signals. The design margins of the matched delays can be small since they are internal to the PLAs, which are regular structures and therefore more predictable.