Serial-link bus: a low-power on-chip bus architecture

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus CB architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus SLB, transforms an n-bit conventional parallel-line bus into an n/m-line (serial-link) bus. The advantage of serial-link buses is that they have fewer lines, and if the bus width is kept the same, serial- link buses will have larger line width and spacing. Increasing the line width has a twofold reduction effect on the line resistance, as the resistivity of sub-100 nm wires significantly drops as the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m exists that minimizes the bus energy dissipation and maximizes the bus throughput per-unit area. The optimum degree of multiplexing for maximum throughput-per- unit-area and for minimum energy dissipation for the 25-130 nm technologies was determined in this paper. HSPICE simulations show that; for the same throughput-per-unit-area as conventional parallel-line buses, the serial-link bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit bus implemented in an intermediate metal layer of a 50 nm technology and a reduction of 52.7% is projected for the 25 nm technology.