Title :
"Flying-Adder" PLL Based Synchronization Mechanism for Data Packet Transport
Author :
Xiu, Liming ; Clynes, Steve ; Gurrapu, Srikanth ; Haider, Towfique ; Ying, Feng ; Mohammed, Wahed
Author_Institution :
Texas Instruments Inc, Dallas, Texas, USA, limingxiu@ti.com
Abstract :
A novel frequency synthesis architecture, Flying-Adder architecture, has been developed in recent years. Compared with conventional PLL based frequency synthesis techniques, this new method has many unique features. Among them, the two most distinguishing ones are its instantaneous response speed and very fine frequency resolution. These features can be especially beneficial to application of data smoothing in packet-oriented transport systems. In this paper, this Flying-Adder PLL based synchronization approach is demonstrated through two real examples.
Keywords :
Clocks; Codecs; Frequency synchronization; Frequency synthesizers; Instruments; Phase locked loops; Smoothing methods; Streaming media; Universal Serial Bus; Voltage-controlled oscillators; Flying-Adder; MEPG2; PLL; USB; data packet; data smoothing; data synchronization; isochronous;
Conference_Titel :
System-on-Chip, 2007. DCAS 2007. 6th IEEE Dallas Circuits and Systems Workshop on
Conference_Location :
Dallas, TX, USA
Print_ISBN :
978-1-4244-1680-6
Electronic_ISBN :
978-1-4244-1680-6
DOI :
10.1109/DCAS.2007.4433203
