DocumentCode
280132
Title
VLSI residue arithmetic architecture for signal processing applications
Author
Arambepola, Bernard
Author_Institution
Dept. of Electr. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
fYear
1990
fDate
33024
Firstpage
42522
Lastpage
42527
Abstract
Residue number arithmetic is a technique for mapping an integer computation into several parallel and independent computations requiring much shorter wordlengths. In this paper the authors present an architecture for carrying out modulo arithmetic in a practically useful residue number system. An important feature of this is that it allows a single hardware design to be used for all moduli. They describe an application of this architecture for computing inner-products in convolutions, transforms and matrix-vector operations
Keywords
VLSI; digital arithmetic; digital signal processing chips; parallel architectures; VLSI residue arithmetic architecture; convolutions; hardware design; inner-products; integer computation; matrix-vector operations; modulo arithmetic; parallel computations; residue number system; signal processing applications; transforms;
fLanguage
English
Publisher
iet
Conference_Titel
VLSI Signal Processing Architectures, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
190294
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