3D source/drain doping optimization in Multi-Channel MOSFET

Author

Tachi, K. ; Vulliet, N. ; Barraud, S. ; Guillaumot, B. ; Maffini-Alvaro, V. ; Vizioz, C. ; Arvet, C. ; Campidelli, Y. ; Gautier, P. ; Hartmann, J.-M. ; Skotnicki, T. ; Cristoloveanu, S. ; Iwai, H. ; Faynot, O. ; Ernst, T.

Author_Institution

CEA-LETI, Minatec, Grenoble, France

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

368

Lastpage

371

Abstract

We demonstrate that the integration of in-situ doped Si Source and Drain (S/D) in three-dimensional Multi-Channel Field-Effect Transistors (MCFETs) leads to improved electrical performances. The combination of in-situ doped Selective Epitaxial Growth (SEG) and ion implantation indeed enables to drastically reduce the S/D resistance (down to 72 Ω.μm for nFET and 227 Ω.μm for pFET). Ion implantation induces a small mobility degradation, which becomes negligible in short gate length (L_G) MCFETs. Gate width down-scaling otherwise needed to suppress the overall mobility degradation with L_G and obtain the best electrical properties.

Keywords

MOSFET; elemental semiconductors; ion implantation; silicon; 3D source-drain doping optimization; Si; ion implantation; multichannel MOSFET; nFET; pFET; selective epitaxial growth; three-dimensional multichannel field-effect transistors; Degradation; Doping; Ion implantation; Logic gates; Performance evaluation; Silicon; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Conference_Location

Sevilla

ISSN

1930-8876

Print_ISBN

978-1-4244-6658-0

Type

conf

DOI

10.1109/ESSDERC.2010.5618209

Filename

5618209