Title :
A reconfigurable fault-tolerant hypercube architecture with global sparing
Author :
Chau, Siu-Cheung ; Fu, Ada Wai-Chee
Author_Institution :
Dept. of Phys. & Comput., Wilfrid Laurier Univ., Waterloo, Ont., Canada
Abstract :
We propose a new n-dimensional fault-tolerant hypercube architecture. We use (n-1) switching networks to connect the N=2n active processors and k spare processors to form an n-dimensional fault-tolerant hypercube. The k spare processors can be used to back-up any k processor failures in the fault-tolerant hypercube. We call such a method global sparing and it is optimal in terms of the number of processor failures that can be back-up by k spare processors. The new architecture can achieve a higher level of reliability using less hardware compared to previously proposed schemes
Keywords :
fault tolerant computing; hypercube networks; reconfigurable architectures; switching networks; global sparing; reconfigurable fault-tolerant hypercube architecture; reliability; switching networks; Computer architecture; Computer science; Costs; Electronic mail; Fault tolerance; Fault tolerant systems; Hardware; Hypercubes; Physics computing; Switches;
Conference_Titel :
Dependable Computing, 2000. Proceedings. 2000 Pacific Rim International Symposium on
Conference_Location :
Los Angeles, CA
Print_ISBN :
0-7695-0975-4
DOI :
10.1109/PRDC.2000.897298