A Parallel Architecture for Radix-2 Fast Fourier Transform

Author

Philipov, Ph ; Lazarov, V. ; Zlatev, Z. ; Ivanova, M.

Author_Institution

Inst. for Parallel Data Process., Bulgarian Acad. of Sci., Sofia

fYear

2006

fDate

3-6 Oct. 2006

Firstpage

229

Lastpage

234

Abstract

This paper describes the main problems, connected with the parallel implementation of the fast Fourier transform (FFT) algorithm on different high-performance computer architectures. Discussed is a possibility for the FFT parallel realization on a parallel architecture, suitable for implementation on field programmable gate arrays (FPGA) and based on perfect shuffle interconnection pattern. Discussed are the main properties of the architecture and similarities with the scalar case. Analyzed are the problems of parameterization and automatic generation of the architecture

Keywords

digital arithmetic; fast Fourier transforms; field programmable gate arrays; mathematics computing; parallel algorithms; parallel architectures; field programmable gate arrays; high-performance computer architectures; parallel architecture; parallel implementation; perfect shuffle interconnection pattern; radix-2 fast Fourier transform; Computational modeling; Computer architecture; Data processing; Discrete Fourier transforms; Fast Fourier transforms; Field programmable gate arrays; Parallel architectures; Programmable logic arrays; Signal processing algorithms; Switches; Highperformance computer architectures.; Parallel Fast Fourier Transform;

fLanguage

English

Publisher

ieee

Conference_Titel

Modern Computing, 2006. JVA '06. IEEE John Vincent Atanasoff 2006 International Symposium on

Conference_Location

Sofia

Print_ISBN

0-7695-2643-8

Type

conf

DOI

10.1109/JVA.2006.4

Filename

4022066