• DocumentCode
    2804609
  • Title

    A Partitioning Technique of General Combinational Circuit Into a Tree Type Circuit

  • Author

    Ali, Samia A.

  • Author_Institution
    Department of Electrical Engineering, North Carolina A & T State University
  • fYear
    1992
  • fDate
    1-3 Mar 1992
  • Firstpage
    116
  • Lastpage
    119
  • Keywords
    Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Computational complexity; Logic testing; Partitioning algorithms; Programmable logic arrays; Read only memory; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Theory, 1992. Proceedings. SSST/CSA 92. The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design
  • ISSN
    0094-2898
  • Print_ISBN
    0-8186-2665-8
  • Type

    conf

  • DOI
    10.1109/SSST.1992.712205
  • Filename
    712205
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2804609