Title :
Comparison of strained SiGe heterostructure-on-insulator (001) and (110) PMOSFETs: C - V characteristics, mobility, and ON current
Author :
Pham, A.T. ; Jungemann, C. ; Meinerzhagen, B.
Author_Institution :
BST, Tech. Univ. Braunschweig, Braunschweig, Germany
Abstract :
For the simulations of C -V characteristics and mobilities a homogenous channel HOI PMOS structure is simulated. The thicknesses of the top and bottom oxide are 1 nm and 10 nm, respectively. The thicknesses of the channel stack layers are tsSi(cap) = 2 nm, tsSiGe = 20 nm, and tsSi = 4 nm. The thickness of the bulk layer below the bottom oxide is 800 nm. The Ge contents in the strained Si1-zGez layer and in the relaxed Si1-yGey virtual substrate are z = 0.46 and y = 0.25, respectively. A uniform donor doping concentration of 1015cm-3 is assumed in in both the channel layers and the bulk Si region. A metal gate contact and an ohmic contact at the bottom of the bulk region are assumed. A bulk bias VB of 0 V and a constant lattice temperature of 300 K are assumed in all simulations. The simulations are performed for the two interface orientations (001) and (110). The channel directions for the (001) and (110) interface orientations are [110] and [-110], respectively.
Keywords :
Ge-Si alloys; MOSFET; ohmic contacts; semiconductor materials; silicon-on-insulator; C-V characteristics; PMOSFET; SiGe; channel stack layers; constant lattice temperature; homogenous channel HOI PMOS structure; metal gate contact; ohmic contact; size 1 nm; size 10 nm; size 2 nm; size 20 nm; size 4 nm; size 800 nm; strained heterostructure-on-insulator; temperature 300 K; uniform donor doping concentration; voltage 0 V; Logic gates; MOSFETs; Metals; Silicon; Silicon germanium; Strain; Substrates;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Conference_Location :
Sevilla
Print_ISBN :
978-1-4244-6658-0
DOI :
10.1109/ESSDERC.2010.5618379