Title :
Enhancing Computer Engineering Education with Verilog/suo R/ HDL
Author :
Jackson, David Jeff ; Hannah, Sidney Joel
Author_Institution :
Department of Electrical Engineering, The University of Alabama
Keywords :
Computational modeling; Computer architecture; Computer science education; Computer simulation; Design engineering; Hardware design languages; Knowledge engineering; Logic design; Logic testing; Microprocessors;
Conference_Titel :
System Theory, 1992. Proceedings. SSST/CSA 92. The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design
Print_ISBN :
0-8186-2665-8
DOI :
10.1109/SSST.1992.712207
