• DocumentCode
    2805050
  • Title

    Enhancing Computer Engineering Education with Verilog/suo R/ HDL

  • Author

    Jackson, David Jeff ; Hannah, Sidney Joel

  • Author_Institution
    Department of Electrical Engineering, The University of Alabama
  • fYear
    1992
  • fDate
    1-3 Mar 1992
  • Firstpage
    125
  • Lastpage
    128
  • Keywords
    Computational modeling; Computer architecture; Computer science education; Computer simulation; Design engineering; Hardware design languages; Knowledge engineering; Logic design; Logic testing; Microprocessors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Theory, 1992. Proceedings. SSST/CSA 92. The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design
  • ISSN
    0094-2898
  • Print_ISBN
    0-8186-2665-8
  • Type

    conf

  • DOI
    10.1109/SSST.1992.712207
  • Filename
    712207
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2805050