• DocumentCode
    2807077
  • Title

    A Study of Architecture Description Languages from a Model-based Perspective

  • Author

    Qin, Wei ; Malik, Sharad

  • Author_Institution
    Boston Univ., MA
  • fYear
    2005
  • fDate
    Nov. 2005
  • Firstpage
    3
  • Lastpage
    11
  • Abstract
    Owing to the recent trend of using application-specific instruction-set processors (ASIP), many architecture description languages (ADLs) have been created. They specify architectures or microarchitectures of processors, and automate tasks including circuit implementation, simulation, retargetable compilation and formal verification. This paper first gives an overview of the existing ADLs. This paper argues that for an ADL to be capable of rigorously specifying a processor, it must be based on a solid foundation which we call the architecture model. The existing ADLs feature a wide variety of formal and ad-hoc architecture models which confines the flexibility and analyzability of the ADLs in one way or another. This paper then discusses the operation state machine (OSM) model, the result of our first attempt to create high-level processor models. The model has features balanced flexibility and analyzability for use in architecture space exploration frameworks for ASIPs. This paper also describes the use of the OSM model in the Mescal architecture description language (MADL), an open-source ADL framework that we developed. Lastly, it points out the potential application of formal verification techniques on OSM
  • Keywords
    formal verification; instruction sets; microcomputers; public domain software; Mescal architecture description language; application-specific instruction-set processors; architecture space exploration; circuit implementation; formal verification; open-source framework; operation state machine; retargetable compilation; Application specific processors; Architecture description languages; Circuit simulation; Circuit testing; Computational modeling; Computer architecture; Formal verification; Instruction sets; Microarchitecture; Solids;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on
  • Conference_Location
    Austin, TX
  • ISSN
    1550-4093
  • Print_ISBN
    0-7695-2627-6
  • Type

    conf

  • DOI
    10.1109/MTV.2005.2
  • Filename
    4022222