Expedient methodology for the quantification of interconnect-induced semiconductor substrate noise

A methodology is proposed for the quantification and analysis of interconnect-induced noise in semiconductor substrates. The methodology is based on the utilization of commonly-used two-dimensional interconnect parasitics extractors together with SPICE-like simulators. Thus, the proposed model offers a convenient alternative to the use of three-dimensional field solvers for the expedient investigation of the attributes and potential consequences of interconnect-induced substrate noise on on-chip signal integrity.