Fast copper plating process for TSV fill

In next generation IC packaging, 3D interconnect has been considered to be the solution not only for footprint shrinkage, but also for integration of different functional devices into one package. The heart of 3D silicon-based technology is Cu filled vias which allow shortest chip-to-chip interconnections. The technology of choice today to make these Cu vias is by electroplating. Even though electroplating Cu for interconnects is a well known technology owing to its wide use in Cu damascene, it proves to be quite a different ball game for through silicon via fill, where via diameter changes from nm to tens of microns and via depth changes from sub microns to hundreds of microns. What we have learned from Cu damascene and what works there could not be applied directly to through silicon via fill. In this paper, we will describe the main hurdles to overcome in achieving a perfect, defect-free fill with minimum overburden and the methodologies to reduce the fill time.