Underfill selection strategy for low k, high lead/lead-free flip chip application

The trend of low k dielectrics for 45 nm silicon technologies is driving the development of new packaging processes and materials. Underfill material is the most critical material in the flip chip packages. The role of underfill is to protect solder joint and fragile low k chip dielectric layers. Generally, solder joints required stiff and rigid underfill but low k layers require more compliant properties. Hence, the underfill material and its associated processes play a big role in determining the reliability of the silicon in the package. New underfill materials have been recently developed to minimize the die stress and prevent low k layer delamination while concurrently reducing the strains on the solder joints. This paper discusses material issues encountered in the development of underfill materials for low k, high lead/lead free applications. The numerous of candidates spends lot of time on reliability testing. A selection strategy is used to characterize and to identify the few favorable underfills that have a high probability of successfully meet our reliability requirements. The process includes use of simulation and mechanical property test methods. Finally, the selection process identified few underfills for package qualification testing.