A new short memory turbo code with good BER performance and low decoding complexity

Author

Liao, Yu

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

5

fYear

2003

fDate

6-9 Oct. 2003

Firstpage

3179

Abstract

A new rate 1/2 turbo code with short memory 2 is developed in this paper. The proposed turbo code consists of two 4-state parallel concatenated non-punctured systematic rate-2/3 convolutional codes. Using a modified maximum a posteriori (MAP) decoding algorithm working on dual codes, its bit error rate (BER) performance is comparable to that of the classic 16-state turbo code at short block lengths, such as k=1024, while its decoding complexity is less than 1/8 that of the classic 16-state turbo codes; for information block length k=504, its BER performance is better than that of the (1008, 3, 6) LDPC codes with comparable decoding complexity. The dual code decoding algorithm is intrinsically partial parallel and a considerably higher throughput of the turbo decoder can be obtained compared with classic turbo codes consisting of punctured codes. The simulation results show that the proposed turbo code can be a competitive technique for short block length applications.

Keywords

concatenated codes; convolutional codes; dual codes; error statistics; maximum likelihood decoding; turbo codes; 4-state parallel concatenated nonpunctured systematic rate-2/3 convolutional code; bit error rate; dual code decoding algorithm; maximum a posteriori decoding algorithm; short memory turbo code; Bit error rate; Concatenated codes; Convolutional codes; Decoding; Degradation; Error correction codes; Hardware; Parity check codes; Throughput; Turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Vehicular Technology Conference, 2003. VTC 2003-Fall. 2003 IEEE 58th

ISSN

1090-3038

Print_ISBN

0-7803-7954-3

Type

conf

DOI

10.1109/VETECF.2003.1286219

Filename

1286219