DocumentCode
2809448
Title
Design on SOC module-level functional verification platform
Author
Zhang, He ; Wu, Chunyu ; Zhang, Wenjing ; Wang, Jiwei
Author_Institution
Coll. of Phys., Liaoning Univ., Shenyang, China
fYear
2011
fDate
15-17 July 2011
Firstpage
4012
Lastpage
4015
Abstract
In the traditional IP verification methodology, module level verification platform have limitations such as uncontrollability, low efficiency, huge workload, long verification time and poor reusability. To resolve these problems, a SOC function verification virtual platform based on bus transaction level strategy is proposed. The virtual verification platform is composed of system component function models, which are described by high level abstraction modeling methods. The platform provides incentives in bus transaction mode based on simulation. The experimental results of practical application show that the platform can improve IP verification efficiency and enhance IP verification reusability. The practical construction and methodology can be used in other function verification platform.
Keywords
industrial property; system-on-chip; IP verification methodology; IP verification reusability enhancement; SOC module-level functional virtual verification platform; bus transaction mode; component function models; high level abstraction modeling methods; intellectual property verification methodology; system on chιp; Conferences; Decoding; Hardware design languages; IP networks; System-on-a-chip; Viterbi algorithm; SOC; function verification; verification platform;
fLanguage
English
Publisher
ieee
Conference_Titel
Mechanic Automation and Control Engineering (MACE), 2011 Second International Conference on
Conference_Location
Hohhot
Print_ISBN
978-1-4244-9436-1
Type
conf
DOI
10.1109/MACE.2011.5987881
Filename
5987881
Link To Document