DocumentCode
280993
Title
Experience of designing JTAG ASICS within System X
Author
Borland, Andrew
Author_Institution
Switching Networks & Control Bus. Centre, GPT, Poole, UK
fYear
1990
fDate
33226
Firstpage
42491
Lastpage
42493
Abstract
Describes some of the experience gained when using the Boundary Scan technique, as proposed by the Joint Test Action Group (JTAG), for Application Specific Integrated Circuit (ASIC) design at GEC Plessey Telecommunication (GPT) in Poole; and offers some thoughts on the advantages and disadvantages of the JTAG method
Keywords
application specific integrated circuits; logic design; ASICS; Boundary Scan technique; GEC Plessey Telecommunication; JTAG; JTAG method; Joint Test Action Group; System X;
fLanguage
English
Publisher
iet
Conference_Titel
Application and Development of the Boundary-Scan Standard, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
191486
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