An ATE architecture for implementing very high efficiency concurrent testing

With the spread of SOC and SIP devices, the independence of IP core operations inside devices have recently been increasing, and there has been growing demand for concurrent testing. In this paper, we propose an Automatic Test Equipment (ATE) architecture that implements concurrent testing with true parallel execution. This architecture makes concurrent testing easy to develop and achieves very high concurrent efficiency. It also exhibits very high multi-site efficiency when used in combination with multi-site testing. It is therefore expected to substantially reduce the Cost of Test (CoT). To confirm these effects, we present experimental results using four mixed-signal devices in both multi-site testing and concurrent testing. We also discuss some applications of the proposed scheme.