Low power Viterbi Decoder by modified ACSU architecture and clock gating method

The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital wireless communication channels, enabling reliable transmission over noisy and fading channel. This requires low power decoders as they consume lot of power. Power reduction in any system can be achieved at device level, at circuit level or at architectural level. In this paper, power reduction is achieved at architecture level. A Viterbi Decoder (VD) with architectural modification for Add-Compare-Select Unit (ACSU) and clock gated Survivor Memory Unit (SMU) are designed for low power wireless applications. A decoder system with code rate of k/n=1/2 with constraint length K=7 has been implemented with 130nm technology. It is synthesized using design compiler of Synopsys and its power is estimated with power compiler. A throughput of 125 Mbps is achieved satisfying the requirement for wireless applications. Bit error rate of proposed system is same as that of modified register exchange VD. Around 66% power is reduced with clock gating technique.