DocumentCode
2812545
Title
Research and Application of All Digital Phase-Locked Loop
Author
Zhang, Qiang ; Huang, Kai ; Liu, Zuojun ; Li, Zhigang
Author_Institution
Sch. of Electr. Eng. & Autom., Hebei Univ. of Technol., Tianjin, China
fYear
2009
fDate
1-3 Nov. 2009
Firstpage
122
Lastpage
125
Abstract
The structure of an all digital phase-locked loop technology, ADPLL, is proposed in this paper. And the digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The time order graphs of all modules are presented. In the way of linear approximation, the first-order and second-order mathematic models of ADPLL are given, as well as the control methods. The feasibility of the ADPLL is proved by simulation. Finally the ADPLL, miss-lock detector and scanning generator circuits are assembled in the FPGA are applied in an inductive heating system. This new ADPLL simplifies the structure of the control system. And the reliability is improved.
Keywords
circuit reliability; digital filters; digital phase locked loops; field programmable gate arrays; oscillators; phase detectors; ADPLL; FPGA; all digital phase-locked loop; digital filter loops; digital phase detector; digital-controlled oscillators; first-order mathematic model; inductive heating system; linear approximation; miss-lock detector; reliability; scanning generator circuits; second-order mathematic model; time order graphs; Assembly systems; Circuit simulation; Detectors; Digital filters; Digital-controlled oscillators; Linear approximation; Mathematical model; Mathematics; Phase detection; Phase locked loops; Digital Loop Filter; Digital-controlled Oscillator; Phase Detector; all digital phase-locked loop;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Networks and Intelligent Systems, 2009. ICINIS '09. Second International Conference on
Conference_Location
Tianjin
Print_ISBN
978-1-4244-5557-7
Electronic_ISBN
978-0-7695-3852-5
Type
conf
DOI
10.1109/ICINIS.2009.40
Filename
5363087
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