• DocumentCode
    28134
  • Title

    An Enhanced Statistical Analysis Method for I/O Links Considering Supply Voltage Fluctuations and Intersymbol Interference

  • Author

    Jingook Kim ; Jongjoo Lee ; Eunkyeong Park ; Youngwoo Park

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Ulsan Nat. Inst. of Sci. & Technol., Ulsan, South Korea
  • Volume
    5
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    1129
  • Lastpage
    1141
  • Abstract
    Statistical link analysis methods were previously developed for effective computation of bit error rate due to intersymbol interference (ISI). In addition to ISI, supply voltage fluctuations at output drivers can cause jitter and amplitude uncertainty in I/O links. In this paper, the enhanced statistical link analysis method considering both ISI and supply voltage fluctuations is clearly reformulated and experimentally validated step by step by various measurements. A silicon integrated circuit (IC) is designed, fabricated, and assembled on a manufactured printed circuit board (PCB). The supply voltage fluctuations on the IC with regard to the receiver reference voltage are extracted from measurements at the IC and PCB. Also, the impulse response of the total output channel is extracted from the measurements of the driver and channel characteristics. The statistical eye diagrams of the channel output including both ISI effects and the supply voltage fluctuations are then calculated and validated by comparison with the direct eye measurements.
  • Keywords
    driver circuits; elemental semiconductors; error statistics; integrated circuit design; intersymbol interference; printed circuit design; reference circuits; silicon; statistical analysis; transient response; I/O links; PCB; Si; bit error rate; channel characteristics; driver characteristics; impulse response; intersymbol interference; manufactured printed circuit board; receiver reference voltage; silicon integrated circuit design; statistical eye diagrams; statistical link analysis; supply voltage fluctuations; Bit error rate; Capacitors; Jitter; Semiconductor device measurement; System-on-chip; Voltage measurement; Bit error rate (BER); linear driver; power distribution network (PDN); power-supply voltage fluctuations; power-supply-induced jitter; probability density function (PDF); signal integrity; statistical link analysis; statistical link analysis.;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2015.2450723
  • Filename
    7173030