DocumentCode
2814517
Title
Increasing the size of atomic instruction blocks using control flow assertions
Author
Patel, Sanjay J. ; Tung, Tony ; Bose, Satarupa ; Crum, Matthew M.
Author_Institution
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fYear
2000
fDate
2000
Firstpage
303
Lastpage
313
Abstract
For a variety of reasons, branch-less regions of instructions are desirable for high-performance execution. In this paper we propose a means for increasing the dynamic length of branch-less regions of instructions for the purposes of dynamic program optimization. We call these atomic regions frames and we construct them by replacing original branch instructions with assertions. Assertion instructions check if the original branching conditions still hold. If they hold, no action is taken. If they do not, then the entire region is undone. In this manner an assertion has no explicit control flow. We demonstrate that using branch correlation to decide when a branch should be converted into an assertion results in atomic regions that average over 100 instructions in length, with a probability of completion of 97%, and that constitute over 80% of the dynamic instruction stream. We demonstrate both static and dynamic means for constructing frames. When frames are built dynamically using finite sized hardware, they average 80 instructions in length and have good caching properties
Keywords
cache storage; computer architecture; performance evaluation; atomic instruction blocks; branch instructions; caching properties; control flow assertions; dynamic length; dynamic program optimization; high-performance execution; Computer aided instruction; Hardware; Optimizing compilers; Proposals; Size control;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 2000. MICRO-33. Proceedings. 33rd Annual IEEE/ACM International Symposium on
Conference_Location
Monterey, CA
ISSN
1072-4451
Print_ISBN
0-7695-0924-X
Type
conf
DOI
10.1109/MICRO.2000.898080
Filename
898080
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