An ultra-fast parallel architecture using sequential circuits computing on random bits

Digital computation on stochastic bit streams is a non-conventional type of computation, which uses digital circuits to process probabilistic inputs. In this paradigm, digital circuits compute on the probability values. This leads to extremely simple digital implementations for complex arithmetic operations. The combinational logic-based designs can be implemented in parallel to realize fast computation by trading off silicon area with delay. However, it is impossible to implement the current sequential logic-based designs in parallel to reduce delay, since they need to compute for a large number of clock cycles to obtain the result. In this work, we propose a novel design methodology for synthesizing sequential circuits that compute on stochastic bit streams, which does not require a long computation delay. We further demonstrate a parallel implementation based on our design, which provides ultra-fast arithmetic computation.