Title :
The Impact of Layout on Stress-Enhanced Transistor Performance
Author :
Moroz, V. ; Eneman, G. ; Verheyen, P. ; Nouri, F. ; Washington, L. ; Smith, L. ; Jurczak, M. ; Pramanik, D. ; Xu, X.
Author_Institution :
Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA 94043, USA. Email: victor.moroz@synopsys.com
Abstract :
This paper studies the sensitivity of stress-enhanced transistor performance to layout variations. Stress simulations and mobility models are calibrated and verified for test structures with SiGe source/drain as a stressor. The role of STI on the stress transfer is explored. The numerical results show that variations of 15% in drive currents and of 44% in hole mobility due to layout induced stress variations can occur in the cases studied. These deviations need to be taken into account in circuit design or to be compensated via layout modification.
Keywords :
Compressive stress; Germanium silicon alloys; Lattices; MOSFETs; Numerical simulation; Silicon germanium; Testing; Thermal expansion; Thermal stresses; Transistors;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on
Print_ISBN :
4-9902762-0-5
DOI :
10.1109/SISPAD.2005.201493
