The Buffer Depth Analysis of 2-Dimension Mesh Topology Network-on-Chip with Odd-Even Routing Algorithm

The network-on-chip (NoC) has been recognized as a paradigm to solve system-on-chip (SoC) design challenges, due to many of the problems that will be faced by the designers of multi-billion transistor chips. The infrastructure of network tail determines system performance and cost. The virtual channel buffer depth of tail´s input channel is one of the key design problems. The deep input channel buffer depth, which is at each tail in the NoC, increases the overall area of chips. At the same time, depending on the network workload, increasing the buffer size can reduce the network latency by orders of magnitude. This paper analyses the buffer depth of 2-dimension mesh topology NoC with odd-even routing algorithm based on NoC interconnect routing and application modeling (NIRGAM) simulator. The analysis results reveal that the optimized input first-in-fist-out (FIFO) buffer depth of virtual channel has not relationship with network scale for 2-dimension mesh topology NoC at constant bit rate (CBR) traffic condition. The optimized input FIFO buffer depth of virtual channel is all 6 for 2×2, 3×3 and 4×4 mesh topology NoC.