FinFET Source/Drain Profile Optimization Considering GIDL for Low Power Applications

We have investigated sub-50nm FinFET design to be used in low power applications, through 3D device simulations considering gate-induced drain leakage (GEDL). It is found that the body-tied structure is necessary for dopedchannel FinFET to reduce off-state current (Ioff). For further reduction of Ioffincluding GIDL, optimization of source/drain (S/D) profile characterized by lateral spread σ and lateral offset δ is effective, and feasibility of S/D profile depends on channel doping concentration. By adjusting the concentration properly, loff can be reduced for (σ,δ) points in a wide range. In addition, sensitivity of drive current upon σ and δ is found to be small.