An Extensible Memory Simulation Framework for Chip Multi-Processors

As the chip multi-processors (CMPs) becoming more attractive for high performance computing, key design decisions especially concerning memory hierarchy should be made more carefully. However, the existing micro-architecture simulators and software tools merely meet the needs of on-chip memory performance modeling. This paper presents a new pin-tool-based memory simulation framework for CMP, called gsim, which is intrinsically extensible with perfect support for widely used x86 ISA. The gsim is time-efficient with ignorable accuracy loss and can be easily extended for memory behavior evaluation and onchip design space exploration.