DocumentCode
2819280
Title
Sigma delta ADC design using Verilog-A
Author
Mannozzi, F. ; Tinfena, F. ; Fanucci, L.
Author_Institution
Dipt. di Ingegneria dell´´Informazione, Pisa Univ.
Volume
1
fYear
2003
fDate
30-30 Dec. 2003
Firstpage
55
Abstract
Electrical simulation gives a good evaluation of the performances of sigma-delta modulators but could require too long simulation times. In this paper we introduce the use of Verilog-A, which provides the capability to model the circuit topology of sigma-delta modulators closely to the electrical level and achieving a considerable reduction of simulation time
Keywords
integrated circuit design; network topology; sigma-delta modulation; Verilog-A; analog-digital converter; circuit topology; electrical simulation; sigma delta ADC design; sigma-delta modulator; Analytical models; Circuit noise; Circuit simulation; Circuit topology; Delta-sigma modulation; Hardware design languages; Integrated circuit interconnections; Noise shaping; Performance analysis; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Conference_Location
Cairo
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562217
Filename
1562217
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