Efficient LDPC decoder implementation for DVB-S2 system

Author

Tsai, Chung-Jin ; Chen, Mu-Chung

Author_Institution

Product Design Div. V, Sunplus Technol. Co., Ltd., Taiwan

fYear

2010

fDate

26-29 April 2010

Firstpage

37

Lastpage

40

Abstract

Low Density Parity Check (LDPC) codes have been adopted in many communication standards in recent years due to their Shannon limit approaching performance. More than that, many standards adopt long block length LDPC codes to achieve better performance. Calculation units are, therefore, increased significantly. Traditional simplified algorithm is not suitable for cutting edge transmission of high quality multimedia data because of the serious performance degradation. Better performance with minimum compensation architecture must be realized. This paper is to present the compensation architecture with minimum added circuits.

Keywords

broadcasting; compensation; forward error correction; multimedia communication; parity check codes; DVB-S2 system; LDPC decoder; Shannon limit; compensation architecture; low density parity check; multimedia data transmission; Circuits; Code standards; Degradation; Digital video broadcasting; Forward error correction; Hardware; Iterative algorithms; Iterative decoding; Parity check codes; Satellite broadcasting; LDPC decoder; Low Density Parity Check (LDPC) codes; compensation architecture; early termination; normalization; shrinking;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Conference_Location

Hsin Chu

Print_ISBN

978-1-4244-5269-9

Electronic_ISBN

978-1-4244-5271-2

Type

conf

DOI

10.1109/VDAT.2010.5496686

Filename

5496686