VLSI circuit architectures for Fermat number arithmetic in DSP applications

Efficient VLSI techniques are presented for implementing arithmetic operations modulo a Fermat number. An architecture based on these techniques is briefly described for computing discrete convolutions and correlations. The object is to consider number theoretic transforms (NTTs) as an alternative to the time domain techniques currently being used in implementing convolution devices. For NTTs to be more efficient than time domain techniques it is necessary to develop efficient VLSI techniques to implement the arithmetic operations of NTTs. Such methods are presented for the most important NTT, namely, the Fermat number transform. A review of this transform is included and a VLSI convolution architecture that can be implemented using these arithmetic circuits is discussed