Diagnostic test generation for small delay defect diagnosis

Small delay defect is becoming an important defect mechanism that leads to yield loss and performance hit in high performance VLSI designs. Small delay defects usually cause a small number of failures in production test patterns, and hence provide little evidence for logic fault diagnosis to isolate a defect. In this paper, we present a diagnostic test generation technique that targets creating more tester failures for a small delay defect in order to improve the diagnostic resolution. Experimental results show the effectiveness of the proposed technique.