A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration

A 12-bit 30-MS/s pipelined ADC is realized using single-stage, low-gain, switched class-AB amplifiers. Nonlinear errors due to finite gain are addressed using a deterministic digital background calibration scheme that employs amplifier duty-cycling to minimize the power overhead. The presented ADC occupies an active area of 0.36 mm² in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near Nyquist. The corresponding figure of merit is 72 fJ/conversion-step.