A simulation study of the Viterbi and Viterbi carrier phase estimation algorithm

To simplify the design of the onboard processor for communication satellites it is desirable to synchronise all transmissions to within a very small fraction of a symbol interval. Power- and spectrum-efficiency considerations have led to a preference for QPSK modulation, with coherent demodulation. An open-loop solution is being studied, with the carrier phase being determined independently for each burst. The (digital) carrier phase estimation algorithm proposed by Viterbi and Viterbi (1983) is ideally suited for this purpose. A single phase estimate can be obtained and used for the whole burst (which is delayed digitally). No preamble is required either for carrier recovery or (because the system is clock synchronous) for the clock. A computer simulation study of the performance of the algorithm is reported. The algorithm and its properties are described, and results from existing literature are summarised. The modelling approach and the creation of the simulation model are also described