• DocumentCode
    282262
  • Title

    Knowledge based test strategy planning

  • Author

    Dislis, C. ; Dear, I.D. ; Lau, S.C. ; Ambler, A.P.

  • Author_Institution
    Brunel Univ., Uxbridge, UK
  • fYear
    1989
  • fDate
    32818
  • Firstpage
    42401
  • Lastpage
    42405
  • Abstract
    As ICs get larger and increasingly more expensive to test, it is becoming clear that testing provision has to be made at the design stage. Brunel University are developing a Knowledge Based Test Strategy Planner, which also takes into account cost considerations. The aim is to provide designers with the advice and means for introducing an effective, realistic test plan for integrated circuits
  • Keywords
    VLSI; circuit CAD; integrated circuit testing; knowledge based systems; Brunel University; IC design; Knowledge Based Test Strategy Planner; cost considerations;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Algorithmic and Knowledge Based CAD for VLSI, IEE Colloquium on
  • Conference_Location
    London
  • Type

    conf

  • Filename
    198924
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=282262