A low-power orthogonal current-reuse amplifier for parallel sensing applications

We demonstrate a low-noise CMOS amplifier array using orthogonal bias current-reuse to improve fundamental noise-power trade-offs. The architecture presented uses stacking to share bias current among the input differential pairs of four amplifiers. By using the output drain currents of each differential pair as tail currents for the next stage, we save bias current. By arranging the stacked differential pairs appropriately, we generate 16 output currents that encode the original inputs in a linearly independent (orthogonal) fashion. These outputs are then recombined in much lower power output stages to reconstruct amplified versions of the inputs. Our design was built in standard 130nm CMOS and has a noise efficiency factor (NEF) of 2.7, close to the lowest published for a differential amplifier. However, amortizing bias current across the 4 parallel amplifier paths in the NEF calculation yields an effective NEF of 1.54. The input-referred noise ranges from 14.5 ßV_rms to 17.4 /iV_rm. between amplifiers in the stack over bandwidths of 426 kHz to 530.2 kHz while consuming a total power of 19.6 μ-W, or 4.9 μW per path. Orthogonal biasing avoids cross-talk between stacked amplifier paths, providing isolation of 37 dB or better.