A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX

Author

Murphy, David ; Gu, Qun Jane ; Wu, Yi-Cheng ; Jian, Heng-Yu ; Xu, Zhiwei ; Tang, Adrian ; Wang, Frank ; Lin, Yu-Ling ; Chen, Ho-Hsiang ; Jou, Chewnpu ; Chang, Mau-Chung Frank

Author_Institution

EE Dept., Univ. of California, Los Angeles, CA, USA

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

258

Lastpage

261

Abstract

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting a 802.15.3c heterodyne TRX is reported. The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF. Phase noise is measured directly at the LO frequency and is better than -97.5dBc/Hz@1MHz across the entire band. The total power consumption is 72mW from a 1V supply. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the LO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic. Central to the PLL performance is the design of a low-noise, mm-wave VCO with a 22.9% tuning range. It is noted that resonator nonlinearities may result in significant up-conversion of flicker noise in wideband, mm-wave VCOs. To overcome this, Digitally-Controlled-Artificial-Dielectric (DiCAD) is used to linearize the resonator.

Keywords

CMOS integrated circuits; personal area networks; phase locked loops; resonators; voltage-controlled oscillators; DiCAD; VCO; compact CMOS PLL; digitally-controlled-artificial-dielectric; frequency 43.2 GHz to 51.84 GHz; heterodyne 802.15.3c TRX; low phase noise; resonator; voltage 1 V; wideband CMOS PLL; CMOS integrated circuits; Phase locked loops; Phase noise; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2010 Proceedings of the

Conference_Location

Seville

ISSN

1930-8833

Print_ISBN

978-1-4244-6662-7

Type

conf

DOI

10.1109/ESSCIRC.2010.5619880

Filename

5619880