DocumentCode
2824593
Title
Design method of defect-tolerant WSI systems based on the residue number system
Author
Tomabechi, Nobuhiro
Author_Institution
Hachinohe Inst. of Technol., Japan
fYear
1991
fDate
11-14 Jun 1991
Firstpage
3082
Abstract
A design method is proposed for defect-tolerant WSI arithmetic systems based on the RNS (residue number system). The yield analysis has shown that the features of the RNS are very well suited for the defect recovery of WSIs. In the RNS, addition and multiplication are performed in parallel, but division is relatively complex. The proposed method seems to be most effectively used for such systems as matrix calculation and signal processing in which high speed operation is essential and division is not as frequently used
Keywords
VLSI; digital arithmetic; fault tolerant computing; microprocessor chips; RNS; addition; arithmetic systems; defect recovery; defect-tolerant WSI systems; design method; high speed operation; matrix calculation; multiplication; residue number system; signal processing; yield analysis; Arithmetic; Circuit testing; Design methodology; Error correction; Hardware; Power system reliability; Production; Redundancy; Very large scale integration; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176199
Filename
176199
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